1. Field of the Invention
This invention relates to a novel circuit for use in conjunction with the ALUs of computers, mini-computers, micro-computers, or microprocessors to permit use thereof for parity check functions, masking functions and the like.
2. Description of the Prior Art
Present arithmetic logic units (ALUs) in computers, mini-computers, micro-computers or microprocessors allow operation of the exclusive OR function only in a bit by bit fashion between two input words to their respective ALUs. The problem is that the exclusive OR operation for all bits within a data word requires many exclusive OR instructions and shift instructions. It is therefore an advantage over prior art systems and a purpose of the present invention to provide circuitry for use in conjunction with the ALU circuits of the prior art computers, mini-computers, micro-computers or microprocessors which will permit their use to provide parity checking, masking and the like in conjunction with a single operation and/or instruction. Such operation will allow the computation or error detecting and correcting codes with an efficiency not attainable using the prior art ALUs.